Kontron AT8050 User Manual download pdf (Page 42)

26 AT8050

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2.12 FPGA

The FPGA has many functions. One of them is to act as a companion chip to the IPMC. The states of all the

critical signals controlled by the IPMC are memorized in the FPGA and are preserved while the IPMC firmware

is being updated.

The FPGA is a RAM-based chip that is preloaded from a separate flash memory at power-up. Two such flash

memory devices are provided; one that can only be programmed in factory and the other one that can be

updated in the field. The factory flash is selected by inserting jumper JP1 pins 3-4. Field updates require to

cycle the power of the board. The IPMI LED2 will blink if the factory flash is being used.

The FPGA update complies to PICMG HPM.1 specification and is remotely updatable via any IPMC channel.

2.13 Telecom Clock Option

The telecom clock option is not shown on the main block diagram. The circuit is made of MLVDS buffers, a PLD

and a multi-service line card PLL. The PLD is hooked to the main FPGA with a fast serial link and from there, to

the IPMC via a proprietary bus.

The PLD receives 19.44MHz clocks from the backplane (CLK2A and CLK2B) and use it as a reference to the

DPLL. Anyone of the PLL clock outputs can be used to feed the AMC’s TCLKA using the FPGA interface. If a

backplane clock is lost, the circuit will automatically switch to the redundant clock. If all backplane clocks are

lost, the PLL will switch to holdover mode until a clock reappears. If both copies of the 19.44MHz from CLK2A

and CLK2B are lost, the clock control circuitry activates an alarm to the IPMC as long as the telecom sync

option is enabled in the shelf.

The PLD is field upgradeable. If upgrade is necessary for this device, an appropriate procedure will be

provided with the code update.

Refer to the register description in appendix and to the ZL30108 datasheet available on Zarlink's web site

(www.zarlink.com

)for further details on possible clock speed and configuration.

2.14 Redundant IPMC Firmware & BootBlock

The IPMC runs a firmware from its internal 512KB flash. The IPMC Boot Block saves the last two copies of the

IPMC firmware image in dedicated SPI flash memory. The Boot Block manages the IPMC reprogramation and

can rollback to the previous firmware image in the IPMC internal flash in case of update problem.

Note:

The IPMC has an external hardware watchdog

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Kontron AT8050 User Manual Page 42