KTD-N0793-O Page 30
3.4.2 LVDS Flat Panel Connector (LVDS)
Note 1: The KTGM45 on-board LVDS connector supports single and dual channel, 18/24bit SPWG panels
up to the resolution 1600x1200 or 1920x1080 and with limited frame rate some 1920x1200.
Signal Description – LVDS Flat Panel Connector:
Backlight control (1), PWM signal to implement voltage in the range 0-3.3V
Backlight Enable signal (active low) (2)
LCDVCC
VCC supply to the flat panel. This supply includes power-on/off sequencing.
The flat panel supply may be either 5V DC or 3.3V DC depending on the CMOS
configuration. Maximum load is 1A at both voltages.
Note 1: Windows API will be available to operate the BKLTCTL signal. Some Inverters have a limited voltage
range 0- 2.5V for this signal: If voltage is > 2.5V the Inverter might latch up. Some Inverters
generates noise on the BKLTCTL signal, resulting in making the LVDS transmission failing
(corrupted picture on the display). By adding a 1Kohm resistor in series with this signal, mounted in
the Inverter end of the cable kit, the noise is limited and the picture is stable.
Note 2: If the Backlight Enable is required to be active high then, check the following BIOS Chipset setting:
Backlight Signal Inversion = Enabled.
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