Kontron KTQM67-mITX User Manual Page 47
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KTQM67 Users Guide
KTD-N0819-K Page 47
6.4.2 LVDS Flat Panel Connector (LVDS) (J20)
Two graphic pipes are supported; meaning that up to two independent displays can be implemented
using any two of display connectors (IO Area - and Internal connectors) with the exception of the
combination eDP + LVDS.
Note
Type
Signal
PIN
Signal
Type
Note
Max. 0.5A
PWR
+12V
1
2
+12V
PWR
Max. 0.5A
Max. 0.5A
PWR
+12V
3
4
+12V
PWR
Max. 0.5A
Max. 0.5A
PWR
+12V
5
6
GND
PWR
Max. 0.5A
Max. 0.5A
PWR
+5V
7
8
GND
PWR
Max. 0.5A
Max. 0.5A
PWR
LCDVCC
9
10
LCDVCC
PWR
Max. 0.5A
2K2Ω, 3.3V
OT
DDC CLK
11
12
DDC DATA
OT
2K2Ω, 3.3V
3.3V level
OT
BKLTCTL
13
14
VDD ENABLE
OT
3.3V level
3.3V level
OT
BKLTEN#
15
16
GND
PWR
Max. 0.5A
LVDS
LVDS A0-
17
18
LVDS A0+
LVDS
LVDS
LVDS A1-
19
20
LVDS A1+
LVDS
LVDS
LVDS A2-
21
22
LVDS A2+
LVDS
LVDS
LVDS ACLK-
23
24
LVDS ACLK+
LVDS
LVDS
LVDS A3-
25
26
LVDS A3+
LVDS
Max. 0.5A
PWR
GND
27
28
GND
PWR
Max. 0.5A
LVDS
LVDS B0-
29
30
LVDS B0+
LVDS
LVDS
LVDS B1-
31
32
LVDS B1+
LVDS
LVDS
LVDS B2-
33
34
LVDS B2+
LVDS
LVDS
LVDS BCLK-
35
36
LVDS BCLK+
LVDS
LVDS
LVDS B3-
37
38
LVDS B3+
LVDS
Max. 0.5A
PWR
GND
39
40
GND
PWR
Max. 0.5A
Note: The KTQM67 on-board LVDS connector supports single and dual channel, 18/24bit SPWG
panels up to the resolution 1600x1200 or 1920x1080 and with limited frame rate some
1920x1200.
Signal Description – LVDS Flat Panel Connector:
Signal
Description
LVDS A0..A3
LVDS A Channel data
LVDS ACLK
LVDS A Channel clock
LVDS B0..B3
LVDS B Channel data
LVDS BCLK
LVDS B Channel clock
BKLTCTL
Backlight control (1), PWM signal to implement voltage in the range 0-3.3V
BKLTEN#
Backlight Enable signal (active low) (2)
VDD ENABLE
Output Display Enable.
LCDVCC
VCC supply to the display. Power-on/off sequencing depending on selected (in BIOS
setup) display type. 5V or 3.3V selected in BIOS setup. LCDVCC is shared with eDP
connector. Maximum load is 1A at both voltages.
DDC CLK
DDC Channel Clock
Notes: Windows API will be available to operate the BKLTCTL signal. Some Inverters have a limited
voltage range 0- 2.5V for this signal: If voltage is > 2.5V the Inverter might latch up. Some
Inverters generates noise on the BKLTCTL signal, resulting in making the LVDS transmission
failing (corrupted picture on the display). By adding a 1Kohm resistor in series with this signal,
mounted in the Inverter end of the cable kit, the noise is limited and the picture is stable.
If the Backlight Enable is required to be active high then, check the following BIOS Chipset
setting: Backlight Signal Inversion = Enabled.
Internal Connectors
- KTQM67 Users Guide 1
- Document revision history 2
- Copyright Notice: 2
- Trademark Acknowledgement: 2
- Disclaimer: 2
- Life Support Policy 2
- Services 3
- Warranty 3
- Contents 4
- Introduction 7
- 1 Installation procedure 8
- Installation procedure 9
- 2 System Specification 10
- 2.2 System overview 14
- 2.3 Processor Support Table 16
- 2.4 System Memory support 19
- 2.5.3 LVDS and DVI 21
- 2.5.4 Graphics Adapters 21
- 2.6 Power Consumption 22
- 3 Connector Locations 30
- 3.3 KTQM67/mITX - backside 31
- 3.4 KTQM67/Flex 32
- 3.5 KTQM67/Flex - backside 33
- 3.6 KTQM67/ATXP 34
- 3.7 KTQM67/ATXP - backside 35
- 4 Connector Definitions 36
- 5 IO-Area Connectors 37
- 5.2 Ethernet Connectors 39
- 6 Internal Connectors 43
- 6.6 USB Connectors (USB) 50
- 6.10 Audio Connectors 55
- 7.1 PCIe Connectors 66
- 7.2 PCI Slot Connectors 71
- Onboard/mating connector 74
- 9 System Resources 75
- 9.2 PCI Devices 76
- 9.3 Interrupt Usage 77
- 9.4 IO Map 78
- System Resources 79
- 10 BIOS 80
- 10.2 Advanced 81
- BIOS - Advanced 100
- 10.3 Chipset 118
- BIOS - Chipset 119
- 10.4 Boot 138
- BIOS - Boot 139
- 10.5 Security 142
- BIOS -Security 143
- 10.6 Save & Exit 146
- 11 AMI BIOS Beep Codes 147
- 12 OS Setup 148
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